S1C88650 8-bit single chip microcomputer original architecture core cpu large-capacity font rom for kanji, simplified chinese and hangul (896k bytes) dot-matrix lcd driver (126 32) description the S1C88650 is an 8-bit microcomputer for portable equipment with an lcd display that has a built-in lcd controller/driver and a character generator (kanji) rom. this microcomputer features low-voltage (1.8v) and high-speed (8.2mhz) operations as well as low-current consumption (2.5? during standby). the lcd control- ler/driver contains an lcd drive power supply circuit and can drive an maximum of 126 32-dot lcd panel in low-power consumption. an 896k-byte large-capacity font rom is embedded in the S1C88650. this allows applications to contain fonts for simplified chinese characters, hangul characters and user-defined characters as well as 11 12-dot jis level-1, jis level-2 and other kanji fonts without an external expanded font rom. this 8-bit cpu has up to 16mb accessible address space allowing easy implementation of a large data processing application. the S1C88650 is suitable for display modules, portable cd/md, solid audio players, pda, data bank and other applications that required an exclusive lcd driver in conventional systems. features core cpu .............................................. s1c 88 (model3) cmos 8-bit core cpu main (osc3) oscillation circu it ............. cr ystal oscillation circuit/ceramic oscillation circuit 8.2mhz (max.) or cr oscillation circuit 2.2mhz (max.) ( ? 1) sub (osc1) oscillation circuit ............... cryst al oscillation circuit 32.768khz (typ.) or cr oscillation circuit 200khz (max.) ( ? 1) instruction set ........................................ 608 types (usable for multiplication and division instructions) min. instruction execution time ............. 0. 244?ec/8.2mhz (2-clock) internal rom capacity .......................... program rom: 48k bytes font rom: 896k bytes (can be used for a program/data rom) internal ram capacity ........................... ram: 8k bytes display memory: 768 bytes bus line ................................................. addr ess bus:20 bits (also usable as a general output port when not used as a bus) data bus: 8 bits (also usable as a general i/o port when not used as a bus) ce signal: 3 bits wr signal: 1 bit rd signal: 1 bit input port ............................................... 8 bits (4 bits can be used as the source clock inputs for pwm timers and 1 bit as a bus request signal input) output port ............................................ 0? bits (when the external bus is used) 26 bits (when the external bus is not used) (1 bit can be configured for the bus acknowledge signal output) i/o port .................................................. 8 bits (when the external bus is used) 16 bits (when the external bus is not used) (shard with serial interface, fout and tout terminals) serial interface ...................................... 1 ch. (optional clock synchronous system or asynchronous system) timer ..................................................... programmable timer: 16 bits (8 bits 2) 4 ch. (with pwm function) clock timer: 1 ch. low voltage operation products (also usable as a general output port when not used as a bus)
2 S1C88650 lcd drive r ............................................. dot matrix type (16 16/5 8 or 12 12 dot fonts) 126 segments 32, 16 or 8 commons ( ? 2) (1/5 bias) built-in lcd power supply circuit (booster type, 5 potentials) watchdog timer ..................................... built-in (0.5? second cycles) supply voltage detection (svd) circuit .... 13 value programmable (1.8v to 2.7v) interrupt ................................................. external interrupt: input port interrupt 1 system (8 types) internal interrupt: timer interrupt 2 systems (16 types) serial interface interrupt 1 system (3 types) supply voltage ...................................... 1.8v to 3.6v current consumption (typ.) .................. sleep mode: 1? halt mode (32khz crystal oscillation, lcd off): 2.5? halt mode (32khz cr oscillation, lcd off): 10? run (32khz crystal oscillation, lcd off): 9? run (32khz cr oscillation, lcd off): 15? run (8.2mhz ceramic oscillation, lcd off): 1700? run (2.2mhz cr oscillation, lcd off): 600? supply form ........................................... qfp8-256pin or chip ? 1: can be selected with mask option ? 2: can be selected with software block diagram core cpu s1c88 interrupt controller system controller input port oscillator osc1, 2 osc3, 4 reset/test reset test watchdog timer k00?02 k03 (breq) k04?07 i/o port serial interface external memory interface output port programmable timer /event counter clock timer power generator ram 8k bytes excl0?xcl3 (k04?07) tout0?out3 (p14, p15) tout2/tout3 (p17) p00?07 (d0?7) p10 (sin) p11 (sout) p12 (sclk) p13 (srdy) r00?07, r10?17, r20?23 (a0?7, a8?15, a16?19) r24, r25 (rd, wr) r30?32 (ce0?e2) r33 (back) seg0?eg125 com0?om31 p14 (tout0/tout1) p15 (tout2/tout3) p16 (fout) p17 (tout2/tout3) v dd v ss v d1 v d2 v c1 ? c5 ca?g lcd driver rom 48k bytes+896k bytes supply voltage detector mcu/mpu breq (k03) back (r33)
3 S1C88650 pin layout diagram qfp8-256pin 129 192 65 128 index 64 1 256 193 S1C88650 pin description pin no. v dd v ss v d1 v d2 v c1 v c5 ca?g osc1 osc2 osc3 osc4 mcu/mpu k00?02 k03/breq k04/excl0 k05/excl1 k06/excl2 k07/excl3 r00?07/a0?7 r10?17/a8?15 r20?23/a16?19 r24/rd r25/wr r30?32/ce0?e2 r33 (back) p00?07/d0?7 p10/sin p11/sout p12/sclk p13/srdy p14/tout0/tout1 p15/tout2/tout3 p16/fout p17/tout2/tout3 com0?om31 seg0?eg125 reset test test pin name in/out function 131, 189 67, 134, 195, 253 135 113 125?21 120?14 136 137 132 133 140 148?46 145 144 143 142 141 165?72 173?80 181?84 185 186 187, 188, 196 197 164?57 156 155 154 153 152 151 150 149 198?13, 112?7 214?52, 4?1, 68?6 139 138 3 i o i o i i i i i i i o o o o o o o i/o i/o i/o i/o i/o i/o i/o i/o i/o o o i i power supply (+) terminal power supply (gnd) terminal internal logic system and oscillation system voltage regulator output terminals lcd circuit power voltage booster output terminal lcd drive voltage output terminals lcd and power voltage booster capacitor connection terminals osc1 oscillation input terminal (select crystal/cr oscillation by mask option) osc1 oscillation output terminal osc3 oscillation input terminal (select crystal/ceramic/cr oscillation by mask option) osc3 oscillation output terminal mcu/mpu mode setup terminal input terminals (k00?02) input terminal (k03) or bus request signal input terminal (breq) input terminal (k04) or programmable timer external clock input terminal (excl0) input terminal (k05) or programmable timer external clock input terminal (excl1) input terminal (k06) or programmable timer external clock input terminal (excl2) input terminal (k07) or programmable timer external clock input terminal (excl3) output terminals (r00?07) or address bus (a0?7) output terminals (r10?17) or address bus (a8?15) output terminals (r20?23) or address bus (a16?19) output terminal (r24) or read signal output terminal (rd) output terminal (r25) or write signal output terminal (wr) output terminals (r30?32) or chip enable signal output terminals (ce0?e2) output terminal (r33) or bus acknowledge signal output terminal (back) i/o terminals (p00?07) or data bus (d0?7) i/o terminal (p10) or serial i/f data input terminal (sin) i/o terminal (p11) or serial i/f data output terminal (sout) i/o terminal (p12) or serial i/f clock i/o terminal (sclk) i/o terminal (p13) or serial i/f ready signal output terminal (srdy) i/o terminal (p14) or programmable timer underflow signal output terminal (tout0/tout1) i/o terminal (p15) or programmable timer underflow signal output terminal (tout2/tout3) i/o terminal (p16) or clock output terminal (fout) i/o terminal (p17) or programmable timer underflow inverted signal output terminal (tout2/tout3) lcd common output terminals lcd segment output terminals initial reset input terminal test input terminal test terminal (open during normal operation)
S1C88650 notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 2003, all right reserved. seiko epson corporation electronic devices marketing division ic marketing & engineering group ed international marketing department 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5117 epson electronic devices website document code: 404813200 issue october, 2003 printed in japan l http://www.epsondevice.com basic external connection diagram k00ek02 k03 (breq) k04ek07 r00er07 (a0ea7) r10er17 (a8ea15) r20er23 (a16ea19) r24 (rd) r25 (wr) r30er32 (ce0ece2) r33 (back) p00ep07 (d0ed7) p10 (sin) p11 (sout) p12 (sclk) p13 (srdy) p14 (tout0/tout1) p15 (tout2/tout3) p16 (fout) p17 (tout2/tout3) symbol x'tal1 c g1 r cr1 x'tal2 ceramic rf c g2 c d2 r cr3 c 1 c 2 c 3 c 4 c 5 c 6 c 7 ec 9 c 10 c 11 c p cres name crystal oscillator trimmer capacitor resistor for cr oscillation crystal oscillator ceramic oscillator feedback resistor gate capacitor drain capacitor resistor for cr oscillation capacitor between v ss and v d1 capacitor between v ss and v c1 capacitor between v ss and v c2 capacitor between v ss and v c3 capacitor between v ss and v c4 capacitor between v ss and v c5 booster capacitors capacitor between v ss and v d2 booster capacitor capacitor for power supply capacitor for reset terminal recommended value 32.768 khz, ci(max.) = 35 k 0e25 pf 1.5 m 4 mhz 4 mhz 1 m 15 pf (crystal oscillation) 30 pf (ceramic oscillation) 15 pf (crystal oscillation) 30 pf (ceramic oscillation) 40 k 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 3.3 f 0.47 f recommended values for external parts lcd panel 126 x 32 v ss osc1 osc2 osc3 osc4 v d1 v c1 v c2 v c3 v c4 v c5 ca cb cc cd ce v d2 cf cg reset v dd test 1: osc1 = crystal oscillation 3: osc3 = crystal or ceramic oscillation 2: osc1 = cr oscillation 4: osc3 = cr oscillation c g2 c g1 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 11 x'tal1 rf cres 3 v c p + - seg0 seg125 com0 com31 x'tal2 or ceramic r cr3 r cr1 c d2 2 1 3 4 S1C88650 [the potential of the substrate (back of the chip) is v ss .] note: the above table is simply an example, and is not guaranteed to work.
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